Non-volatile memory device and method of fabricating the same

ABSTRACT

A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode. Using the sidewall spacer and the gate electrode, the stack insulating layer is etched to form a charge storage layer that protrudes from the sidewall of the gate electrode.

RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.10/186,153, filed on Jun. 27, 2002, now pending, which relies forpriority upon Korean Patent Application No. 2001-37420, filed on Jun.28, 2001, the contents of which are herein incorporated by thisreference in their entirety.

FIELD OF THE INVENTION

The present invention generally relates to a method of fabricating asemiconductor device. More specifically, the present invention isdirected to a floating trap-type non-volatile memory device that storesdata in a charge storage layer including one insulating layer byinjecting charges, and to a method of fabricating the same.

BACKGROUND OF THE INVENTION

Non-volatile memory devices continuously hold data even when an externalpower is turned off. As the integration density of memory devicesincreases, there is a need for reducing the area and vertical height ofa memory cell. Since a conventional floating gate type non-volatilememory device has a floating gate, it is restrictive to reduce avertical height of a memory cell. For that reason, a floating trap-typenon-volatile memory device has been attractive as a candidate toovercome the above disadvantage in that charges can be stored in atleast one insulating layer without a floating gate.

FIG. 1 is a top plan view of a conventional floating trap-typenon-volatile memory device. A device isolation layer 11 is formed in apredetermined area of a semiconductor substrate to define an activeregion 13. A plurality of gate electrodes 30 cross the active region,and a charge storage layer 24 is intervened between the gate electrode30 and the active region 13. A sidewall spacer 36 is formed on asidewall of the gate electrode 30.

FIG. 2 through FIG. 5 are cross-sectional flow diagrams showing thesteps of fabricating a conventional nonvolatile memory device, takenalong a line I-I′ of FIG. 1.

Referring now to FIG. 2, a device isolation layer 11 is formed in apredetermined area of a semiconductor substrate to define active regions13. A stack insulating layer 18 and a gate conductive layer 20 areformed on a semiconductor substrate where the device isolation layer 11is formed. Generally, the stack insulating layer 18 includes first,second, and third insulating layers 12, 14, and 16 which areconventionally made of thin thermal oxide, silicon nitride, and CVDoxide, respectively.

Referring now to FIG. 3, the gate conductive layer 20 and the stackinsulating layer 18 are sequentially patterned to form a plurality ofgate electrodes 30 crossing the device isolation layer 11. A tunneloxide layer 22, a charge storage layer 24, and a blocking insulatinglayer 26 are sequentially stacked between the gate electrode 30 and theactive region 13. In case sidewalls of the tunnel oxide layer 22, thecharge storage layer 24, and the blocking insulating layer 26 aredamaged by an etch, a defect density increases with increased trapdensity around edges of the tunnel oxide layer 22 and the blockinginsulating layer 26. As a result, it is likely to generate atrap-assisted leakage current to the gate electrode 30 and thesemiconductor substrate 10 through the high-density trap.

Referring now to FIG. 4, a thermal oxidation process is carried out forthe semiconductor substrate in order to alleviate the damage of thesidewalls of the blocking insulating layer 26 and the gate electrode 30.As a result, a capping insulating layer 32 is formed on a sidewall and atop surface of the gate electrode 30.

Referring now to FIG. 5, using the gate electrode 30 and the cappinginsulating layer 32 as an ion implanting mask, impurities are implantedinto the semiconductor substrate to form an impurity diffusion layer 34.A sidewall spacer 36 is then formed on sidewalls of the charge storagelayer 24, the blocking insulating layer 26, and the capping insulatinglayer 32 that are sequentially stacked. As illustrated in FIG. 4 andFIG. 5, oxygen atoms are diffused through an interface between thesemiconductor substrate 10 and the tunnel oxide layer 22 during thethermal oxidation process. At this time, an edge of the tunnel oxidelayer 22 becomes thick (i.e., a bird's beak phenomenon occurs) becauseit is oxidized by the diffused oxygen atoms. This leads to a drop indevice operational speed. Furthermore, a trap density becomes high atthe relatively thicker edge of the tunneling oxide layer 22 therebyincreasing trap-assisted leakage current through the edge. As the bird'sbeak phenomenon causes a thickness variation of a tunnel oxide layer tobe high in a cell array, device characteristics become non-uniform. Themore a gate line width decreases, the more the thickness of the tunneloxide layer 22 increases. Therefore, what is needed is a non-volatilememory device with a structure to overcome device operationalcharacteristic defects that result from a tunnel oxide layer of hightrap density and from bird's beak phenomenon.

SUMMARY OF THE INVENTION

A feature of the present invention is to provide a non-volatile memorydevice having a conformal tunnel oxide layer without a bird's beakphenomenon, and to provide a method of fabricating the same.

Another feature of the present invention is to provide a non-volatilememory device that can minimize the influence of trap-assistedtunneling, and to provide a method of fabricating the same.

According to an aspect of the present invention, a non-volatile memorydevice includes a charge storage layer and a gate electrode. The gateelectrode crosses an active region between device isolation layersformed in a semiconductor substrate. The charge storage layer intervenesbetween the gate electrode and the active region. An edge of the chargestorage layer extends to form a protruding part that protrudes from asidewall of the gate electrode.

In a preferred embodiment of the present invention, the charge storagelayer is isolated by the device isolation layer or is successive underthe gate electrode. A blocking insulating layer intervenes between thegate electrode and the charge storage layer, and a tunnel oxide layerintervenes between the charge storage layer and the active region. Thenon-volatile memory device further includes a first sidewall spacer onboth sidewalls of the gate electrode. The width of the charge storagelayer is preferably approximately equal to the sum of a width of thegate electrode and widths of the first sidewall spacers. Further, thenon-volatile memory device may include a second sidewall spacer thatcovers a sidewall of the charge storage layer and the first sidewallspacer. A gate capping insulating layer may intervene between thesidewall of the gate electrode and the sidewall spacer.

The non-volatile memory device has a cell array region and a peripheralcircuit region. A first transistor including a wordline and a stackinsulating layer is formed on an active region. The stack insulatinglayer comprises a tunnel oxide layer, a charge storage layer, and ablocking insulating layer and a first transistor. A second transistorincluding at least a gate insulating layer and a gate electrode isformed in the peripheral region. The first sidewall spacer may be formedon each sidewall of the gate electrodes in the first and secondtransistors. Further, a second sidewall spacer may be formed on thefirst sidewall spacer that is formed on each sidewall of the wordlineand the gate electrode.

According to another aspect of the present invention, a method offabricating a non-volatile memory device is provided. A stack insulatinglayer is formed on an active region of a semiconductor substrate. Thestack insulating layer comprises at least first, second, and thirdinsulating layers that are sequentially stacked. A plurality of gateelectrodes crossing the active region are formed on a semiconductorsubstrate including the stack insulating layer. The stack insulatinglayer is patterned to form a tunnel oxide layer, a charge storage layer,and a blocking insulating layer that are sequentially stacked betweenthe gate electrode and the active region. The tunneling oxide layer, thecharge storage layer, and the blocking insulating layer correspond tothe first, second, and third insulating layers, respectively. An edge ofthe charge storage layer has a protruding part that protrudes from asidewall of the gate electrode.

Specifically, the device isolation layer may be formed using aconventional trench isolation technology. In this case, the stackinsulating layer is formed on an overall surface of a semiconductorsubstrate where the device isolation layer is formed. A gate conductivelayer is formed on the stack insulating layer, and then is patterned toform a gate electrode crossing the active region. Alternatively, thedevice isolation layer may be formed using a self-aligned trenchisolation technology. In this case, a stack insulating layer and a lowergate conductive layer are sequentially formed on an active regionbetween the device isolation layers. An upper gate conductive layer isformed on an overall surface of a semiconductor substrate where thedevice isolation layer is formed. Thereafter, the upper and lower gateconductive layers are sequentially patterned to form the active regioncrossing the active region.

In a preferred embodiment of the present invention, a first sidewallspacer is formed on a sidewall of the gate electrode so as to form theprotruding part of the charge storage layer. Using the first sidewallspacer and the gate electrode as an etch mask, at least the third andsecond insulating layers are etched to form a blocking insulating layerprotruding from the sidewall of the gate electrode and a charge storagelayer. Alternatively, prior to formation of the first sidewall spacer,the third insulating layer exposed to both sides of the gate electrodemay be removed. In this case, the charge storage layer has a protrudingpart that protrudes from the sidewall of the gate electrode, and thefirst sidewall spacer covers the sidewall of the gate electrode and anupper portion of the protruding part. Further, a second sidewall spacermay be formed to cover sidewalls of the charge storage layer and thefirst sidewall spacer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view of a conventional non-volatile memory device.

FIG. 2 through FIG. 5 are cross-sectional flow diagrams showing thesteps of fabricating the conventional non-volatile memory device, takenalong a line I-I′ of FIG. 1.

FIG. 6 is a top plan view of a non-volatile memory device according tofirst and second embodiments of the present invention.

FIG. 7 is a cross-sectional view of the non-volatile memory deviceaccording to the first embodiment, taken along a line II-II′ of FIG. 6.

FIG. 8 through FIG. 11 are cross-sectional flow diagrams showing thesteps of fabricating the non-volatile memory device according to thefirst embodiment, taken along the line II-II′ of FIG. 6.

FIG. 12 through FIG. 14 are cross-sectional flow diagrams showing thesteps of fabricating the non-volatile memory device according to thesecond embodiment, taken along the line II-II′ of FIG. 6.

FIG. 15 is a top plan view of a non-volatile memory device according tothird and fourth embodiments of the present invention.

FIG. 16 is a cross-sectional view of a non-volatile memory deviceaccording to the third embodiment, taken along a line III-III′ of FIG.15.

FIG. 17 through FIG. 19 are cross-sectional flow diagrams showing thesteps of fabricating the non-volatile memory device according to thethird embodiment, taken along the line III-III′ of FIG. 15.

FIG. 20 is a cross-sectional view of a structure according to the fourthembodiment, taken along the line III-III′ of FIG. 15.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. The invention may, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. It will also be understood that when a layer is referred to asbeing “on” another layer or substrate, it can be directly on the otherlayer or substrate, or intervening layers may also be present. Likenumbers refer to like elements throughout.

FIG. 6 is a top plan view illustrating a non-volatile memory deviceaccording to first and second embodiments of the present invention, inwhich a region “a” is a cell array region and a region “b” is aperipheral circuit region. FIG. 7 is a cross-sectional view illustratingthe non-volatile memory device according to the first embodiment, takenalong a line II-II′ of FIG. 6.

Referring now to FIG. 6 and FIG. 7, a device isolation layer 101 isformed in a predetermined region of a semiconductor substrate 100. Thedevice isolation layer 101 defines a plurality of first active regions103 in the cell array region “a”, and a second active region 203 in theperipheral circuit region “b”. A plurality of wordlines 140 crossingover the first active regions 103 and the device isolation layer 101 areformed in the cell array region “a”. A stack insulating layer intervenesbetween the wordlines 140 and the first active regions 103, and includesa tunnel oxide layer 152, a charge storage layer 154, and a blockinginsulating layer 156 that are sequentially stacked. It is preferablethat the tunnel oxide layer 154, the charge storage layer 154, and theblocking insulating layer 156 are made of thermal oxide, siliconnitride, and CVD oxide, respectively. Also, the blocking insulatinglayer 156 and the charge storage layer 154 overlap with the wordline 140to cross over the first active region 103 and the device isolation layer101. A sidewall of the wordline 140 is covered with a first sidewallspacer.

Furthermore, a gate capping oxide layer 142 may intervene between thewordline 140 and the first sidewall spacer 146. A width of the chargestorage layer 154 is larger than that of the wordline 140 at least, sothat the blocking insulating layer 156 has a protruding part 151protruding from a sidewall of the wordline 140. Therefore, although ahigh electric field is applied between the wordline 140 and the firstactive regions 103 by a program voltage or an erase voltage, an electricfield applied to the protruding part 151 is relatively weak. This causesa conspicuous decrease in a leakage current flowing through a blockinginsulating layer 156 and a tunnel oxide layer 152 that are located overand under the protruding part 151, respectively. As a result, a softprogram characteristic or a data retention characteristic can beimproved.

The first sidewall spacer 146 covers not only the sidewall of thewordline 140 but also a top of the protruding part 151. The secondsidewall spacer 146 may cover an outer sidewall of the first sidewallspacer 148 and a sidewall of the charge storage layer 154. A firstimpurity diffusion layer 150 is formed in the first active region 103between the wordlines 140. Therefore, a first cell transistor is formedat an intersection of the wordline 140 and the first active region 103.In this case, the tunnel oxide layer 152 under the wordline 140 has auniform thickness. That is, a thick tunnel oxide layer caused by abird's beak phenomenon is not formed at least under an edge of thewordline 140. Thus, a plurality of first transistors in the cell arrayregion “a” have the equivalent threshold voltage.

A gate electrode 240 crossing over the second active region 203 isformed in the peripheral circuit region “b”. The first sidewall spacer146 covers the gate insulating layer 202 between the gate electrode 240and the second active region 203, and a sidewall of the gate electrode240. The second sidewall spacer may cover an outer sidewall of the firstsidewall spacer 146. A gate capping layer 142 may intervene between thefist sidewall spacer 142 and the gate electrode 240. A dual-structuredimpurity diffusion layer 254 is formed in the second active region 203at both sides of the gate electrode 240. The dual-structured impuritydiffusion layer 254 includes a second impurity diffusion layer 250 and athird impurity diffusion layer 252 that correspond to a lightly dopedimpurity diffusion layer and a heavily doped impurity diffusion layer,respectively.

FIG. 8 through FIG. 11 are cross-sectional flow diagrams showing thesteps of fabricating a non-volatile memory device according to a firstembodiment of the present invention, taken along a line II-II′ of FIG.6.

Referring now to FIG. 8, a device isolation layer 101 is formed in asemiconductor substrate 100 to define a first active region 103 and asecond active region 203 in a cell array region “a” and a peripheralcircuit region “b”, respectively. A stacking insulating layer 108 and agate conductive layer 120 are sequentially formed in a cell array region“a” of a semiconductor substrate 100 where the device isolation layer101 is formed. At the same time, a gate insulating layer 108 and a gateconductive layer 120 are sequentially formed in a peripheral region “b”of the semiconductor substrate where the device isolation layer 101 isformed. Preferably, the stack insulating layer 108 is formed bysequentially stacking first, second, and third insulating layers 102,104, and 106. Preferably, the first insulating layer 102 is made ofthermal oxide. Preferably, the first insulating layer has a thickness ofapproximately 15 Å-35 Å in order to lower a program and erase voltages.In this embodiment, it is preferable that the second insulating layer104 has a thickness of approximately 40 Å-100 Å, and the thirdinsulating layer 106 has a thickness of approximately 40 Å-120 Å. Thegate conductive layer 120 may be made of polysilicon, or polycide thatis formed by sequentially stacking polysilicon and metal silicide.

Referring now to FIG. 9, the gate conductive layer 120 is patterned toform a plurality of wordlines 140 crossing the first active regions 103in the cell array region “a”, and to form a gate electrode 240 at leaston the second active region 203 in the peripheral circuit region “b”.The third insulating layer 106 exposed between the wordlines 140 isoveretched or attacked by plasma while etching the gate conductive layer120. Therefore, a defect site may be created in the third insulatinglayer around an edge of the wordline 140. Subsequently, a trap-to-traptunneling may occur through the defect site. Charges stored in alater-formed charge storage layer are then discharged to a gateelectrode, having an undesirable influence on device operations.Preferably, in order to overcome the above disadvantages, a thermaloxidation process is performed for a semiconductor substrate where thewordline 140 and the gate electrode 240 are formed. Thus, the damage ofthe third insulating layer 106 can be alleviated. As a result, a gatecapping oxide layer 142 is formed on sidewalls and top surfaces of thewordline 140 and the gate electrode 240.

Referring now to FIG. 10, impurities are implanted into the first activeregion 103 between the wordlines 140 to form a first impurity diffusionlayer 150. Also, impurities are implanted into the second active region203 at both sides of the gate electrode 240 to form a second impuritydiffusion layer 250. Alternatively, the first and second impuritydiffusion layers 150 and 250 may be formed at the same time or prior toformation of the gate capping oxide layer 142. Thereafter, a spacerinsulating layer 144 is conformally formed on an entire surface of theresultant structure in which the first and second impurity diffusionlayers 150 and 250 are formed. Preferably, the spacer insulating layer144 is made of silicon nitride or oxide.

Referring now to FIG. 11, the spacer insulating layer 144 isanisotropically etched to form a first sidewall spacer 146 on sidewallsof the wordline 140 and the gate electrode 240. If the spacer insulatinglayer 144 is made of oxide, the third insulating layer 106 is alsoetched during the anisotropic etch to expose the second insulating layer104. If the spacer insulating layer 144 is made of silicon nitride, thethird insulating layer 106 is etched using the wordline 140 and thefirst sidewall spacer 146 as an etch mask following formation of thefirst sidewall spacer 146.

Using the first sidewall spacer 146 and the gate electrode 140 as anetch mask, at least the second insulating layer 108 is then etched toform at least second and third insulating layer patterns 154 and 156between the wordline 140 and the first active region 103. Edges of thesecond and the third insulating layer patterns 154 and 156 are extendedto form a protruding part 151 that protrudes from both sides of thewordline 140. The second insulating layer patterns 154 correspond to acharge storage layer, and the third insulating layer pattern 156intervened between the wordline 140 and the second insulating layer 154corresponds to a blocking insulating layer. The first insulating layer152 under the wordline 140 corresponds to a tunnel oxide layer.

Following formation of the first sidewall spacer 146, impurities areimplanted into the second active region exposed to both sides of thegate electrode 240 in the peripheral circuit region “b” to form a thirdimpurity diffusion layer 252. Subsequently, a dual-structured impuritydiffusion layer 254 is formed in the second active region at both sidesof the gate electrode 240. The third impurity diffusion layer 252 may beformed before or after formation of the second insulating layer pattern154.

Following formation of the third and the second insulating layerpatterns 156 and 154, a second sidewall spacer 148 (see FIG. 7) mayfurther be formed in the cell array region “a” and the peripheralcircuit region “b”. In the cell array region “b”, the second sidewallspacer 148 covers sidewalls of the first sidewall spacer 146, the thirdinsulating layer pattern 156, and the second insulating layer pattern154. In the peripheral circuit region “b”, the second sidewall spacer148 covers the first sidewall spacer 146. If the second sidewall spacer148 is further formed, the third impurity diffusion layer 252 may beformed in the second active region 203 exposed to both sides of the gateelectrode 240 following formation of the second sidewall spacer 148.Alternatively, the first and second impurity diffusion layers 150 and250 may be formed following the formation of the first sidewall spacer146, and the third impurity diffusion layer 252 may be formed followingthe formation of the second sidewall spacer 148.

As a result, a width of the charge storage layer 158 is equal to the sumof the width of the gate electrode 140 and the widths of the sidewallspacers 146. In other words, the non-volatile memory device of theinvention has a protruding part that is formed by extending an edge ofthe charge storage layer 158 to protrude from a sidewall of the gateelectrode 140. Therefore, even if defect sites are created in insulatinglayers over/under the protruding part, device operation characteristicsare scarcely influenced by the defect sites compared with a prior art.Because an edge of the tunnel oxide layer 152 also protrudes from thegate electrode 140 wherein a bird's beak phenomenon may occur insubsequent annealing processes, the non-volatile memory device of theinvention has an excellent data retention characteristic compared withthe prior art.

FIG. 12 through FIG. 14 are cross-sectional flow diagrams for explainingthe steps of fabricating a non-volatile memory device according to asecond embodiment of the present invention.

Referring now to FIG. 12, steps until formation of a gate conductivelayer 120 (see FIG. 8) in the second embodiment are identical to thosein the first embodiment, as described in FIG. 8. The gate conductivelayer 120 and the third insulating layer 106 (see FIG. 8) aresequentially patterned to form a wordline 140 and a third insulatinglayer pattern 156 a on the second insulating layer 104 in the cell arrayregion “a” and to form a gate electrode 240 in the peripheral circuitregion “b”. The third insulating layer pattern 156 corresponds to ablocking insulating layer. Furthermore, a thermal oxidation process iscarried out for the semiconductor substrate to form a gate capping oxidelayer 142′ on a sidewall and a top surface of the wordline 140 and thegate electrode 240.

Referring now to FIG. 13, in the cell array region “a”, impurities areimplanted into a first active region 103 between the wordlines 140 toform a first impurity diffusion layer 150. In the peripheral circuitregion “b”, impurities are implanted into a second active region 203exposed to both sides of the gate electrode 240 to form a secondimpurity diffusion layer 250. A spacer insulating layer 144 isconformally formed on an entire surface of a semiconductor substrate 100where the wordline 140 and gate electrode 240 are formed. The spacerinsulating layer 144 is made of silicon nitride or oxide.

Referring now to FIG. 14, the spacer insulating layer 144 isanisotropically etched to form a first sidewall spacer 146 on sidewallsof the wordline 140 and the gate electrode 240. If the spacer insulatinglayer 144 is made of silicon nitride, the second insulating layer 104 isalso etched to form the first sidewall spacer 146 and a secondinsulating layer pattern 154 with a protruding part 151 a protrudingfrom the sidewall of the wordline 140 while anisotropically etching thespacer insulating layer 144.

If the spacer insulating layer 144 is made of oxide, it isanisotropically etched to form a first sidewall spacer 146 on thesidewall of the wordline 140. Using the first sidewall spacer 146 andthe gate electrode 140 as an etch mask, the second insulating layer 104is then etched to form a second insulating layer pattern 154 with aprotruding part 151 a protruding from the sidewall of the gate electrode140. The second insulating layer pattern 154 corresponds to a chargestorage layer. Following formation of the first sidewall spacer 146,impurities are implanted into the second active region 203 at both sidesof the gate electrode 240 to form a third impurity diffusion layer 252.As a result, a dual-structured impurity diffusion layer 254 is formed inthe second active region 203 at both sides of the gate electrode 240.The third impurity diffusion layer 252 may be formed after or beforeformation of the second insulating layer pattern 154.

Following formation of the second insulating layer pattern 154, a secondsidewall spacer 148 (see FIG. 7) may further be formed in the cell arrayregion “a” and the peripheral circuit region “b”. In the cell arrayregion “a”, the second sidewall spacer 148 of FIG. 7 covers the firstsidewall spacer 146 and the sidewalls of the third and second insulatinglayer pattern 156 a and 154. In the peripheral circuit region “b”, thesecond sidewall spacer 148 of FIG. 7 covers the first sidewall spacer146. In this case, the third impurity diffusion layer 252 may be formedin the second active region 203 at both sides of the gate electrode 240following formation of the second sidewall spacer 148. Alternatively,the first and second impurity diffusion layers 150 and 250 may be formedfollowing formation of the first sidewall spacer 146, and the thirdimpurity diffusion layer 252 may be formed following the formation ofthe second sidewall spacer 148.

As illustrated in the drawings, constructions of the non-volatile memorydevices according to the first and second embodiments are very similarto each other. A difference therebetween is that the third insulatinglayer pattern 156 a is self-aligned to the wordline 140, and thus awidth of the third insulating layer pattern 156 a is identical to awidth of the wordline 140. Therefore, the first sidewall spacer 146covers a sidewall of the gate electrode 140, a sidewall of the thirdinsulating layer 156 a, and a top surface of the protruding part 151 a.

FIG. 15 is a top plan view illustrating a non-volatile memory deviceaccording to third and fourth embodiments of the present invention, inwhich reference numerals “a” and “b” denote a cell array region and aperipheral circuit region, respectively. FIG. 16 is a cross-sectionalview illustrating a non-volatile memory device according to a thirdembodiment of the present invention, taken along a line III-III′ of FIG.15.

Referring now to FIG. 15 and FIG. 16, a device isolation layer 101′ isformed in a predetermined area of a semiconductor substrate 100 todefine a plurality of first active regions 103′ in the cell array region“a”, and to define a second active region 203′ in the peripheral circuitregion “b”. A plurality of wordlines 183 crossing over the first activeregions 103′ and the device isolation layer 101′ are formed in the cellarray region “a”. A stack insulating layer intervenes between thewordlines 183 and the first active regions 103′, and includes a tunneloxide layer 162, a charge storage layer 194, and a blocking insulatinglayer 196 that are sequentially stacked. It is preferable that thetunnel oxide layer 162, the charge storage layer 194, and the blockinginsulating layer 196 are made of thermal oxide, silicon nitride, and CVDoxide, respectively. A sidewall of the wordline 183 is covered with afirst sidewall spacer 186.

Furthermore, a gate capping oxide layer 182 may intervene between thewordline 183 and the first sidewall spacer 186. Since the charge storagelayer 194 and the blocking insulating layer 196 have larger widths thanthe wordline 183, they have a protruding part 191 that protrudes fromthe sidewall of the wordline 183. Therefore, although a high electricfield is applied between the wordline 183 and the first active region103′ by a program voltage or an erase voltage, an electric field appliedto the protruding part 191 is weak. As a result, a leakage currentflowing through the blocking insulating layer 196 and the tunnel oxidelayer 162 each being formed over and under the protruding part 191 isconsiderably reduced to improve a soft program characteristic or a dataretention characteristic.

The first sidewall spacer 186 covers not only the sidewall of thewordline 183 but also a top surface of the protruding part 191.Furthermore, a second sidewall spacer 188 (see FIG. 19) may cover anouter sidewall of the first sidewall spacer 186, a sidewall of theblocking insulating layer 196, and a sidewall of the charge storagelayer. A first impurity diffusion layer 190 is formed in the firstactive region 103′ between the wordlines 183. Therefore, a first celltransistor is formed at an intersection of the wordline 183 and thefirst active region 103′. In this case, the tunnel oxide layer 152 underthe wordline 140 has a uniform thickness. That is, a thick tunnel oxidelayer caused by a bird's beak phenomenon is not formed at least under anedge of the wordline 183. Thus, a plurality of first transistors in thecell array region “a” have the equivalent threshold voltage.

In the peripheral circuit region “b”, a gate electrode 283 is formed tocross over the second active region 203. A gate insulating layer 262intervenes between the gate electrode 283 and the second active region203. A sidewall of the gate electrode 283 is covered with the firstsidewall spacer 186. Furthermore, an outer sidewall of the firstsidewall spacer 186 may be covered with a second sidewall spacer, asdescribed above. The gate capping oxide layer 182 may intervene betweenthe first sidewall spacer 186 and the gate electrode 283.Dual-structured impurity diffusion layers 294 are formed in the secondactive region 203′ at both sides of the gate electrode 283. Thedual-structure impurity diffusion layer 294 includes second and thirdimpurity diffusion layers 290 and 292. As a result, the impuritydiffusion layer 294 corresponds to an LDD-type source/drain region, andthe second impurity diffusion layer 290 and the third impurity diffusionlayer 292 correspond to a lightly doped diffusion layer and a heavilydoped impurity diffusion layers, respectively.

A difference between the first and third embodiments is that the deviceisolation layer 101′ is formed using a self-aligned shallow trenchtechnology (S. A. STI). Accordingly, the wordline 183 includes an upperwordline 180 crossing the first active region 103′ and a lower wordline181 intervened between the upper wordline 180 and the first activeregion 103′. As shown in FIG. 16, the gate electrode 283 may include alower gate electrode 281 and an upper gate electrode 280.

FIG. 17 through FIG. 19 are cross-sectional flow diagrams for explainingthe steps of fabricating the non-volatile memory device according to thethird embodiment of the present invention, taken along a line III-III′of FIG. 15.

Referring now to FIG. 17, a stack insulating layer 168 is formed on asemiconductor substrate 100. After the stack insulating layer 168 formedin a peripheral circuit region “b” is removed and a gate insulatinglayer 262 is formed, a lower gate conductive layer 169 and a hard masklayer are formed on an entire surface of the substrate 100. The hardmask layer, the lower gate conductive layer 169, the stack insulatinglayer 168, and the substrate 100 in a cell array region “a” and the hardmask layer, the lower gate electrode 169, and the substrate 100 aresequentially patterned to form a trench in a predetermined area of thesubstrate 100. Preferably, the first insulating layer 162 is formed to athickness of 15 Å-35 Å in order to make a tunneling of charges even inlow program and erase voltages. As above-mentioned in the firstembodiment, the second insulating layer 164 is preferably made ofsilicon nitride to a thickness of 40 Å-100 Å, and the third insulatinglayer 166 is preferably made of CVD oxide to a thickness of 40 Å-120 Å.Thereafter, the trench area is filled with an insulating layer to form adevice isolation layer 101′, and the hard mask layer is removed.

Referring now to FIG. 18, the upper gate conductive layer 170 is formedon an entire surface of a semiconductor substrate 100 where the deviceisolation layer 101′ is formed. The upper gate conductive layer 170 ispreferably made of polysilicon, or polycide that is formed bysequentially stacking polysilicon and metal silicide.

Referring now to FIG. 19, the upper gate conductive layer 170 and thelower gate conductive layer 169 are sequentially patterned to form aplurality of wordlines 183 crossing the first active region 103′ in thecell array region “a”, and to form a gate electrode 283 crossing thesecond active region 203′ in the peripheral circuit region “b”. In thesame manner as the first embodiment, a first impurity diffusion layer190 is formed in the first active region 103′ between the wordlines 183,and a second impurity diffusion layer 290 is formed in the second activeregion 203′ at both sides of the gate electrode 283. A first sidewallspacer 186 is formed on sidewalls of a wordline 183 and a gate electrode283. The wordline 183 includes lower and upper wordlines 181 and 180that are sequentially stacked, and the gate electrode 283 includes lowerand upper gate electrodes 281 and 280. Using the sidewall spacer 186 andthe gate electrode 183 in the cell array region “a” as an etch mask, atleast the third and second insulating layers 166 and 164 are etched toform third and second insulating layer patterns 196 and 194 between thegate electrode 183 and each of the active regions 103′.

An edge of the second insulating layer pattern 194 is extended to have aprotruding part 191 that protrudes from a sidewall of the gate electrode183. The second insulating layer pattern 194 corresponds to a chargestorage layer, and the third insulating layer pattern 196 intervenedbetween the wordline 183 and the second insulating layer pattern 194corresponds to a blocking insulating layer. The first insulating layer162 intervened between the second insulating layer pattern 194 and thefirst active region 103′ corresponds to a tunnel oxide layer. Followingformation of the first sidewall spacer 186, impurities are implantedinto the second active region 203′ at both sides of the gate electrode283 in the peripheral circuit region “b” to form a third impuritydiffusion layer 292. Thus, a dual-structured impurity diffusion layer294 is formed in the second active region 203′ on either side (bothsides) of the gate electrode 283. The third impurity diffusion layer 292may be formed before or after formation of the second insulating layerpattern 194.

Furthermore, a second sidewall spacer 188 may be formed in the cellarray region “a” and the peripheral circuit region “b”. The secondsidewall spacer 188 covers not only sidewalls of the third and secondinsulating layer patterns 196 and 194 in the cell array region “a” butalso the first sidewall spacer 186 in the peripheral circuit region “b”.In this case, the first and second impurity diffusion layers 190 and 290may be formed following formation of the first sidewall spacer 186.Also, the third impurity diffusion layer 292 may be formed in the secondactive region 203′ on either side (both sides) of the gate electrode 283following formation of the second sidewall spacer 148.

FIG. 20 is a cross-sectional view illustrating a non-volatile memorydevice according to a modified version of the second embodiment, takenalong a line III-III′ of FIG. 15.

Referring now to FIG. 20, in a fourth embodiment of the invention, adevice isolation layer is formed using a self-aligned shall trenchtechnology (S. A. STI), like the third embodiment. Steps until formationof the gate conductive layer are identical to those in the foregoingmodified version of the first embodiment. Subsequent steps are performedin the same manner as the second embodiment, forming a wordline 183crossing a first active region 103′ in a cell array region “a” of asemiconductor substrate 100 and a gate electrode 283 extended to anupper part of the device isolation layer 101′ in the second activeregion 203′ in the peripheral circuit region “b”. A gate capping oxidelayer 182′ may further be formed on sidewalls and top surfaces ofwordline 183 and gate electrode 283. A tunnel oxide layer 162, a chargestorage layer 194, and a blocking insulating layer 196 a aresequentially stacked on the first active region 103′ between deviceisolation layers 101 a, and are intervened between the wordline 183 andthe first active region 103′. The blocking insulating layer 196 a isself-aligned to the wordline 183, so that their widths are identical toeach other.

A sidewall of the charge storage layer 194 has a protruding part 191 athat protrudes from a sidewall of the gate electrode. A first sidewallspacer 186 is formed on the sidewall of the wordline 183 and theprotruding part 191 a of the charge storage layer 194 in the cell arrayregion “a”, and on the sidewall of the gate electrode 283 in theperipheral circuit region “b”. Furthermore, the second spacer 188 may beformed to cover the first sidewall spacer 186 and a sidewall of thecharge storage layer 194 in the cell array region “a”, and the firstsidewall spacer 186 in the peripheral circuit region “b”. A firstimpurity diffusion layer 190 is formed in the first active region 103′between the wordlines 183, and a dual-structured impurity diffusionlayer 294 is formed in a second active region 203′ on either side (bothsides) of the gate electrode 283. The dual-structured impurity diffusionlayer 294 includes second and third impurity diffusion layers 290 and292.

According to the present invention, an edge of a charge storage layer isextended to have a protruding part that protrudes from a sidewall of agate electrode. With a high defect density, edges of a blockinginsulating layer and a tunnel oxide layer also protrude from thesidewall of the gate electrode, which results in a conspicuous decreasein a leakage current flowing through defect sites in the edges of theblocking insulating layer and the tunnel oxide layer. Thus, a dataretention characteristic can be improved in comparison with the priorart.

Furthermore, the invention makes it possible to lessen deterioration ofrepeated operation cycle characteristics, and to form a tunnel oxidelayer without a bird's beak under the gate electrode. Thus, thethreshold voltage distribution range of memory cells can be reduced.

Those skilled in the art will readily implement the steps necessary toprovide the structures and the methods disclosed herein, and willunderstand that the process parameters, materials, dimensions, andsequence of steps are given by way of example only and can be varied toachieve the desired structure as well as modifications that are withinthe scope of the invention. Variations and modifications of theembodiments disclosed herein may be made based on the description setforth herein, without departing from the spirit and scope of theinvention as set forth in the following claims.

1. A method of fabricating a non-volatile memory device, comprising thesteps of: forming a stack insulating layer on a semiconductor substrateby sequentially stacking first, second and third insulating layers;forming a gate electrode crossing over the stack insulating layer; andforming a charge storage layer and a blocking insulating layer which aresequentially stacked between the gate electrode and the first insulatinglayer by patterning the third and second insulating layers, wherein atleast the second insulating layer is patterned so that the chargestorage layer has a protruding part which protrudes from a sidewall ofthe gate electrode.
 2. The method of claim 1, wherein the first andthird insulating layers are made of silicon oxide, and the secondinsulating layer is made of silicon nitride.
 3. The method of claim 1,wherein the step of forming the charge storage layer and the blockinginsulating layer includes the steps of: etching the third insulatinglayer by using the gate electrode as an etch mask to form a blockinginsulating layer which is self-aligned to the gate electrode; forming afirst sidewall spacer on the sidewall of the gate electrode and asidewall of the blocking insulating layer; and etching the secondinsulating layer by using the gate electrode and the first sidewallspacer as an etch mask to form a charge storage layer whose width islarger than a width of the gate electrode.
 4. The method of claim 3,further comprising a steps of forming a gate capping oxide layer atleast on the sidewall of the gate electrode prior to formation of thefirst sidewall spacer.
 5. The method of claim 3, further comprising astep of forming a second sidewall spacer on an outer sidewall of thefirst sidewall spacer and the sidewall of the charge storage layer. 6.The method of claim 1, wherein the step of forming the charge storagelayer and the blocking insulating layer includes the steps of: forming afirst sidewall spacer on the sidewall of the gate electrode; andsequentially etching third and second insulating layers by using thegate electrode and the first sidewall spacer to form a blockinginsulating layer having a protruding part under the first sidewallspacer and a charge storage layer which is self-aligned to the blockinginsulating layer.
 7. The method of claim 6, further comprising a step offorming a gate capping oxide layer at least on the sidewall of the gateelectrode prior to formation of the first sidewall spacer.
 8. The methodof claim 6, further comprising a step of forming a second sidewallspacer on the outer sidewall of the first sidewall spacer, the sidewallof the blocking insulating layer, and the sidewall of the charge storagelayer.
 9. A method of fabricating a non-volatile memory device,comprising the steps of: forming a device isolation layer and a stackinsulating layer, wherein the device isolation layer is formed in apredetermined area of a semiconductor substrate to define an activeregion, and the stack insulating layer includes first, second and thirdinsulating layers which are sequentially stacked at least on the activeregion; forming a gate electrode crossing the active region on the stackinsulating layer; and forming a charge storage layer and a blockinginsulating layer which are sequentially stacked between the firstinsulating layer and the gate electrode by patterning the third tosecond insulating layers, wherein at least the second insulating layeris patterned so that the charge storage layer has a protruding partwhich protrudes from the sidewall of the gate electrode.
 10. The methodof claim 9, wherein the first and third insulating layers are made ofsilicon oxide, and the second insulating layer is made of siliconnitride.
 11. The method of claim 9, wherein the step of forming thedevice isolation layer, the stack insulating layer, and the gateelectrode includes the steps of: sequentially forming a first insulatinglayer, a second insulating layer, a third insulating layer, and a lowergate conductive layer on an entire surface of the substrate;sequentially patterning the lower gate conductive layer, the thirdinsulating layer, the second insulating layer, and the first insulatinglayer to form a trench region which defines an active region in apredetermined area of the substrate; forming a device isolation layer tofill the trench area; forming a lower gate conductive layer on an entiresurface of a resultant structure including the device isolation layer;and sequentially patterning the upper gate conductive layer and thepatterned lower gate conductive layer to form a lower gate electrodeintervened between the gate electrode and the active region as well asan upper gate electrode crossing over the active region and the deviceisolation layer.
 12. The method of claim 9, wherein the step of formingthe device isolation layer, the stack insulating layer, and the gateelectrode includes the steps of: forming a device isolation layer todefine an active region in a predetermined area of the substrate;sequentially forming first to third insulating layers and a gateconductive layer on an entire surface of a resultant structure includingthe device isolation layer; and patterning the gate conductive layer.13. The method of claim 9, wherein the step of forming the chargestorage layer and the blocking insulating layer includes the steps of:etching the third insulating layer by using the gate electrode as anetch mask to form a blocking insulating layer which is self-aligned tothe gate electrode; forming a first sidewall spacer on the sidewall ofthe gate electrode and the sidewall of the blocking insulating layer;and etching the second insulating layer by using the gate electrode andthe first sidewall spacer as an etch mask to form a charge storage layerwhose width is larger than a width of the gate electrode.
 14. The methodof claim 13, further comprising a step of forming a gate capping oxidelayer at least on the sidewall of the gate electrode prior to formationof the first sidewall spacer.
 15. The method of claim 13, furthercomprising a step of forming a second sidewall spacer on the outersidewall of the first sidewall spacer and the sidewall of the chargestorage layer.
 16. The method of claim 9, wherein the step of formingthe charge storage layer and the blocking insulating layer includes thesteps of: forming a first sidewall spacer on the sidewall of the gateelectrode; and sequentially etching the third and second insulatinglayers by using the gate electrode and the first sidewall spacer as anetch mask to form a blocking insulating layer having a protruding partunder the first sidewall spacer and a charge storage layer which isself-aligned to the blocking insulating layer.
 17. The method of claim16, further comprising a step of forming a gate capping oxide layer atleast on the sidewall of the gate electrode prior to formation of thefirst sidewall spacer.
 18. The method of claim 16, further comprising astep of forming a second sidewall spacer on the outer sidewall of thefirst sidewall spacer, the sidewall of the blocking insulating layer,and the sidewall of the charge storage layer.
 19. A method offabricating a non-volatile memory device with a cell array region and aperipheral circuit region, comprising the steps of: forming not only adevice isolation layer in a predetermined area of a semiconductorsubstrate to define a first active region and a second active region inthe cell array region and the peripheral circuit region, respectively,but also a stack insulating layer including first, second and thirdinsulating layers which are sequentially stacked on the first activeregion, and a gate insulating layer stacked on the second active region;forming a plurality of wordlines crossing over the stack insulatinglayer, and a gate electrode crossing over the gate insulating layer; andpatterning at least the third and second insulating layers to form acharge storage layer and a blocking insulating layer which aresequentially stacked between the first insulating layer and thewordlines, wherein at least the second insulating layer is patterned sothat the charge storage layer has a protruding part which protrudes froma sidewall of the wordlines.
 20. The method of claim 19, wherein thefirst and third insulating layers are made of silicon oxide, and thesecond insulating layer is made of silicon nitride.
 21. The method ofclaim 19, wherein the step of forming the device isolation layer, thestack insulating layer, the gate insulating layer, the wordlines, andthe gate electrode includes the steps of: selectively forming the stackinsulating layer on the substrate in the cell array region; selectivelyforming a gate insulating layer on the substrate in the peripheralcircuit region; forming a lower gate conductive layer under a resultantstructure including the gate insulating layer; sequentially patterningthe lower conductive layer, the stack insulating layer, the gateinsulating layer, and the substrate to form a trench area which definesa first active region and a second active region in the cell arrayregion and the peripheral circuit region, respectively; forming a deviceisolation layer to fill the trench area; forming an upper gateconductive layer on an entire surface of a resultant structure includingthe device isolation layer; and forming a plurality of wordlinescrossing over the upper gate conductive layer, and a gate electrodecrossing over the second active region, wherein each of the wordlinesincludes an upper wordline crossing over the first active region, and alower wordline intervened between the upper wordline and the firstactive region; and wherein the gate electrode includes an upper gateelectrode crossing over the second active region, and a lower gateelectrode intervened between the upper gate electrode and the secondactive region.
 22. The method of claim 19, wherein the step of formingthe device isolation layer, the stack insulating layer, the gateinsulating layer, the wordlines, and the gate electrode includes thesteps of: forming a device isolation layer in a predetermined area ofthe substrate to define a first active region and a second active regionin the cell array region and the peripheral circuit region,respectively; selectively forming first, second and third insulatinglayers in the cell array region of a resultant structure including thedevice isolation layer; forming a gate insulating layer on the secondactive region; forming a conductive layer on an entire surface of aresultant structure including the first to third insulating layers andthe gate insulating layer; and patterning the conductive layer to formwordlines crossing the first active region and a gate electrode crossingthe second active region.
 23. The method of claim 19, wherein the stepof forming the charge storage layer and the blocking insulating layerincludes the steps of: etching the third insulating layer by using thewordlines as an etch mask to form blocking insulating layers which areself-aligned to the wordlines; forming a first sidewall spacer onsidewalls of the wordlines, sidewalls of the blocking insulating layers,and the sidewall of the gate electrode; and etching the secondinsulating layer by using the wordlines and the first sidewall spacer asan etch mask to form a charge storage layer whose width is larger than awidth of the wordline.
 24. The method of claim 23, further comprising astep of forming a gate capping oxide layer on surfaces of the wordlinesand a surface of the gate electrode prior to formation of the firstsidewall spacer.
 25. The method of claim 23, further comprising a stepof implanting impurities into the second active region by using the gateelectrode and the first sidewall spacer as an ion implanting mask toform a heavily doped source/drain region, before or after forming thecharge storage layer.
 26. The method of claim 25, further comprising astep of implanting impurities into the first and second active regionsby using the wordlines and the gate electrode as an ion implanting mask,before or after forming the blocking insulating layer.
 27. The method ofclaim 23, further comprising a step of forming a second sidewall spaceron the outer sidewall of the first sidewall spacer and the sidewall ofthe charge storage layer in the cell array region, and on an outersidewall of the first sidewall spacer in the peripheral circuit region.28. The method of claim 27, further comprising a step of implantingimpurities into the second active region by using the gate electrode,the first sidewall spacer, and the second sidewall spacer as an ionimplanting mask to form a heavily doped source/drain region.
 29. Themethod of claim 28, further comprising a step of implanting impuritiesinto the first and second active regions by using the wordlines and thegate electrode as an ion implanting mask to form a lightly dopedsource/drain region.
 30. The method of claim 28, further comprising astep of implanting impurities into the first and second active regionsby using the wordlines, the gate electrode, and the first sidewallspacer as an ion implanting mask to form a lightly doped source/drainregion.
 31. The method of claim 19, wherein the step of forming thecharge storage layer and the blocking insulating layer includes thesteps of: forming a first sidewall spacer on the sidewalls of thewordlines and the sidewall of the gate electrode; and sequentiallyetching the third and second insulating layers by using the gateelectrode, the first sidewall spacer, and the first sidewall spacer asan etch mask to form a blocking insulating layer having a protrudingpart under the first sidewall spacer and a charge storage layer that isself-aligned to the blocking insulating layer.
 32. The method of claim31, further comprising a step of a gate capping oxide layer on thesurface of the gate electrode and the surfaces of the wordlines prior toformation of the first sidewall spacer.
 33. The method of claim 31,further comprising a step of implanting impurities into the secondactive region by using the wordlines, the gate electrode, and the firstsidewall spacer as an ion implanting mask to form a heavily dopedsource/drain region, following formation of the first sidewall spacer.34. The method of claim 33, further comprising a step of implantingimpurities into the first and second active regions by using thewordlines and the gate electrode as an ion implanting mask to form alightly doped source/drain region, prior to formation of the firstsidewall spacer.
 35. The method of claim 31, further comprising a stepof forming a second sidewall spacer on the outer sidewall of the firstsidewall spacer, the sidewall of the charge storage layer, and thesidewall of the blocking insulating layer in the cell array region, andon the outer sidewall of the first sidewall spacer in the peripheralcircuit region.
 36. The method of claim 35, further comprising a step ofimplanting impurities into the second active region by using the gateelectrode, the first sidewall spacer, and the second sidewall spacer asan ion implanting mask to form a heavily doped source/drain region. 37.The method of claim 36, further comprising a step of implantingimpurities into the first and second active regions by using thewordlines and the gate electrode as an ion implanting mask to form alightly doped source/drain region, prior to formation of the firstsidewall spacer.
 38. The method of claim 36, further comprising a stepof implanting impurities into the first and second active regions byusing the wordlines, the gate electrode, and the first sidewall spaceras an ion implanting mask to form a light doped source/drain region,before or after forming the charge storage layer and the blockinginsulating layer.